Freescale HCS08 VGA output2011-08-12
Recently I built a programmer for HCS08, HCS12 and Coldfire V1 families of Freescale MCUs according to this instruction. I remember working with these MCUs from the university (it's been only half a year since then after all), so the first experiments didn't take too much time and I came to something more advanced - VGA signal generation for a display with analog input.
I used a HCS08 family microcontroller MC9S08JS16CWJ. This MCU has CPU speed of 48 MHz and maximum bus frequency of 24 MHz. Instruction execution speed is derived from the bus frequency. The simplest instructions such as NOP take 1 bus cycle, the other instructions take more cycles, for example RTS takes 6 bus cycles. MC9S08JS16CWJ datasheet mistakenly states that RTS instruction takes 5 bus cycles. It took me some time to find this error. (In the current datasheet, the error is already fixed.)
VGA signal has 5 components. These include horizontal synchronization, vertical synchronization and three analog color signals. Analog color signal range is 0..0.7 V with 75 Ω impedance and sync signals are TTL signals.
I have chosen the resolution 640x480. Detailed description of the VGA video signal can be found on many places, for example here, here, here and here, and I have used this description. There is also a lot of examples of VGA interfacing with different MCUs, for example here and here.
When we want to achieve the refresh rate of 60 Hz at that particular resolution, the pixel clock must be 25.175 MHz. As the MCU bus frequency is 24 MHz, it seems to be the best solution to sync pixels to the bus frequency. The display refresh rate is therefore slightly lower, somewhere around 57 Hz.
The implementation is in the form of an infinite loop, where one loop cycle equals to one video frame. During every frame the video signal is generated line by line.
It is necessary to wait exact amount of cycles between signal level changes. Therefore it was necessary to use assembly to create the program. Waiting is performed by means of NOP instructions. I created basic wait subroutines to wait power of two amount of cycles from 16 to 32768. Assembly source contains wait subroutines in the form of macros, for example sleep125. Implementation of these subroutines and macros is generated using a python script. To reduce the code length, some parts of the code are shared by more subroutines.
A subroutine was created that draws multiple lines, where the number of lines is expected in the A register. Every line is divided into 16 parts. Colors of these parts are stored in RAM. Pointer to this array is expected in the HX register. Each of the 3 color channels is 1 bit only, so the 2^3 = 8 basic colors are available.
Static image isn't too interesting, so I added scrolling strips. It is implemented as a rotating buffer. Some lines of the video signal don't contain analog color signals. During these there is enough time to perform such computation. The source code of the assembly program and the python script is here.
The electric circuit is fairly simple (schematics updated — two caps — C3 and C4 — added to filter away high-frequency noise of the power source). The MCU uses external crystal of 12.000 MHz frequency. Apart from MCU and the crystal there are only 4 resistors, 2 ceramic capacitors and of course a VGA connector to connect the display (I used a VGA cable from an old CRT display, in this case a VGA F-F Gender Changer comes in handy).
DISCLAIMER: THIS INFORMATION, SCHEMATIC AND SOFTWARE IS PROVIDED BY FRANTICWARE ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL FRANTICWARE OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.